1. Field of the Invention
The present invention relates to a circuit board structure with an embedded semiconductor chip and a fabrication method thereof, and more particularly, to a circuit board structure for embedding a semiconductor chip in a circuit board and a fabrication method thereof.
2. Description of the Prior Art
The structure of semiconductor packages and chips is becoming smaller in line with the trend towards high integration. In view of this, a circuit board functioning as a semiconductor chip circuit board (hereinafter referred to as a circuit board or carrier) is generally densely disposed with electrical connection pads in order to allow a semiconductor chip mounted on the circuit board to be electrically connected to the circuit board, thereby allowing the semiconductor chip to operate. To reduce package size, the area occupied by integrated circuits (IC) may be reduced by using high circuit density, multi-pin packages with a ball grid array (BGA) structure, flip chip structure, chip size packages (CSP), or multi-chip modules (MCM). However, before a semiconductor chip is mounted on a circuit board and packaging begins, a connection metal layer is formed on an exposed surface of the electrode pads for the semiconductor chip so as to provide for electrical connection elements, such as gold wires, bumps, and solder balls, for electrical connection with the circuit board, and also to prevent the electrode pads from extrinsically induced oxidation.
FIG. 1 is a schematic view showing how to form in a known manner a connection metal layer on the surfaces of electrode pads of a semiconductor chip. The prior art involves forming a passivation layer 13 on the surface of a semiconductor wafer 1 having undergone a required front-end process and formed with a plurality of electrode pads 12; forming a plurality of openings 130 in the passivation layer 13 to expose the electrode pads 12; electroplating a connection metal layer 14 onto the electrode pads 12 in the openings 130 using an electroplating process; performing a cutting process whereby the semiconductor wafer 1 is cut into a plurality of semiconductor dies, wherein a plurality of connection metal layers 14 are disposed on the electrode pads 12 of the semiconductor dies; and performing a packaging process on the semiconductor dies so as to finalize the outward electrical connection required for the semiconductor dies.
Although the aforesaid prior art enables a connection metal layer to be formed on the surfaces of the electrode pads so as to protect the electrode pads from oxidation and protect the electrode pads on the surface of the semiconductor chip against contamination during a subsequent packaging process performed on the semiconductor chip, electrical quality may be affected due to a surface of the connection metal layer being exposed to and therefore oxidized by air, because the connection metal layer is typically formed by copper electroplating.
Accordingly, a need exists for a solution that simplifies processing, reduces costs, and protects the electrode pads of a semiconductor chip from oxidation or contamination.